1. Field of the Invention
This invention relates generally to the structure and fabrication process of planar power MOSFETs. More particularly, this invention relates to a novel and improved structure and process for fabricating a power MOSFET device without a passivation layer and the field plate for manufacturing MOSFET devices at lower cost.
2. Description of the Prior Art
For a conventional power metal oxide silicon field effect transistor (MOSFET) device, the requirement for employing a passivation layer for preventing the device from being physical damaged and for insulating from mobile ions leads to more complicate fabrication process and a higher production cost. Specifically, the device structure of a conventional MOSFET leaves several openings which are exposed if not protected by a passivation layer. These openings are vulnerable to physical damages and mobile ion contamination. Protection by the use of passivation layer is therefore required for the conventional device structure.
For the purpose of better understanding the limitations encountered in the prior art, general descriptions for the techniques currently employed for fabricating power MOSFET devices are first discussed as background information. FIG. 1 shows a typical vertical double diffused MOS (VDMOS) device which uses a double diffusion technique to control the channel length l. Two successive diffusions are performed with first a p diffusion using boron, then a n diffusion using either arsenic or phosphorous, to produce two closely spaced pn junctions at different depths below the silicon surface. With this pn junction, as shown in FIG. 1, the VDMOS supports the drain voltage vertically in the n.sup.- epilayer. The current flows laterally from the source through the channel, parallel to the surface of the silicon. The current flow then turns through a right angle to flow vertically down through the drain epilayer to the substrate and to the drain contact. The p-type "body" region in which the channel is formed when a sufficient positive voltage is applied, and the n.sup.+ source contact regions are diffused successively through the same window etched in the oxide layer. The channel length can be controlled through the processing steps. Because of the relative doping concentrations in the diffused p- channel region and the n- layer, the depletion layer which supports V.sub.DS, a drain to source voltage, extends down into the epilayer rather than laterally into the channel.
In order to best utilize the silicon, the power MOSFET device is fabricated by employing a cellular structure as that shown in FIGS. 2A and 2B. Several different schemes are used. High current capability is obtained by connecting many cells together in parallel as will be discussed below. As shown in FIG. 2B, heavily doped poly-crystalline silicon is used as gate electrode. For power MOSFETs, it has several advantages because it simplifies the connection metalization process where an oxide layer can be formed over the poly-silicon and the source metalization may then be extended over the whole of the upper surface. The poly silicon, used as gate electrodes, can be deposited with great accuracy and the gate oxide is more stable and less prone to contamination than the aluminum gate. Furthermore, the source is self aligned automatically with the gate edge thus greatly simplifies the fabrication process.
A cross sectional view of a conventional planar cellular structure of power MOSFETs, for different topologies such as square, circular, and hexagonal cell arrangements, is shown in FIG. 3. A power MOSFET device 10 as shown has to be protected by a passivation layer which is typically a PECVD nitride or a PSG passivation layer 15. The passivation layer 15 is necessary to serve as a barrier to block the mobile ions. As shown in FIG. 3, the possible contamination openings A, B, C, other than the source (S), gate (G), the field plate (FP), and the equal potential ring (EQR) surface areas, are protected by the nitride layer 15. Cost savings in manufacturing power MOSFET devices are limited by this conventional structure due to the requirements that a passivation layer and field plate are necessary with this type of device structure, thus involving additional processing steps and adversely impacting the production costs.
Therefore, there is still a need in the art of power device fabrication, particularly for power MOSFET design and fabrication, to provide a structure and fabrication process that would resolve these limitations.